In testing semiconductor IC devices by a semiconductor IC test system (IC tester or tester), the basic procedure of functional testing of a semiconductor IC device contains creation of input (drive) stimulus for the IC device, application of these stimulus and comparison of the output of the IC device with expected results by strobing the outputs at predetermined times. Such input stimulus and strobes are collectively called a test pattern or test vector and are traditionally generated based on test data in a cyclized form. Such a traditional test system is sometimes called a cycle based test system or a cyclized tester where various data for producing the input stimulus and strobes is defined relative to corresponding test cycles (tester rates or timesets).
Today, IC design is made under an electronic design automation (EDA) environment where IC designers develop new ICs with use of a high-level language such as Verilog or VHDL and simulate the design by behavioral, gate-level Verilog/VHDL simulators. Such design simulation is targeted to check the functionality and performance before the design is fabricated into silicon IC. To use the design simulation data, the traditional IC test systems require conversion of design simulation data into cyclized form, such as WGL (Waveform Generation Language) or STIL (Standard Test Interface Language) format.
As noted above, the present day semiconductor IC test systems are single or multiple timesets (cyclized or cycle based) machines, in which data are associated with each pin (T. Kazamaki et al. “Trial model of 100 MHz test station for high speed LSI test system”, IEEE Int. Test Conf., pp. 139–145, 1978, T. Sudo, “A 100 MHz tester—challenge to new horizon of testing high speed LSI ” IEEE Int. Test Conf., pp. 362–368, 1979, and M. Shimizu et al., “100 MHz algorithmic pattern generator for memory testing”, IEEE, Int. Test Conf., pp. 56–67, 1980). The variations are that in some test systems, these timesets can be switched on the fly; in other test systems, waveform formatters are available to generate complex waveforms; and third variation is that relay functionalities are incorporated for shared resource machines in order to share or distribute the timing generators to the desired pins (S. Bisset, “The development of a tester per pin VLSI test system architecture”, IEEE Int. Test Conf., pp. 151–155, 1983).
Because of these timesets and waveform formatters, the operating environment of today's test systems is quite different from the IC design environment. Timesets, waveforms, waveform groups, timing generators, waveform formatters, sequences and pattern bits/pin are manifestations of the test systems and not the IC design. However, because of these limitations in today's test systems, IC testing requires a different environment than the original IC design and simulation environment.
From the user's point of view, the above limitations cause following problems: (i) vector conversion consumes extensive time, server and disk capacities, and is very error-prone, (ii) cyclization of vectors makes multiple clock domain devices untestable, and (iii) due to a finite number of resources such as timesets, waveform groups, timing generators, etc., there arises tester limitations.
While the primary IC design and simulation environment is event oriented, because of the above limitations, the test environment is cyclized. Hence, it is a foreign environment from the original IC design environment and causes difficulties during testing and debug the ICs. Also, to get to the test environment, engineers are required to reformat simulation testbenches and re-run simulation to capture the cyclized vectors that are required for testing. Essentially, it makes the test data very different than the original design and simulation data. The engineers translate vectors into another intermediate format such as STIL (Standard Test Interface Language, IEEE standard 1450, 1999) and WGL (Waveform Generation Language) to create test program as illustrated in FIG. 1A.
FIG. 1A shows a process involved in today's cyclized test systems for testing the IC by using the design testbench data (simulation vectors). In this example, the left side indicates a design domain 10 where the design testbench is executed through a logic simulator thereby producing input/output event data of the design, i.e. VCD (Value Change Dump by Verilog). The right side indicates a test domain 20 where the designed IC device is tested by the IC tester with use of the test vectors produced based on the VCD data produced in the design domain.
As shown in FIG. 1A, in the conventional technology involving the cycle based test system, the test program development requires (i) extracting event based simulation vectors (VCD format) at step 11, (ii) converting the simulation vectors into cycle based vectors at step 12, and (iii) converting the cycle based vectors into tester's format such as WGL and STIL at step 21 and/or a proprietary format such as TDL (“Test Description Language” by Advantest Corporation, Tokyo, Japan) at step 22. The resultant test vectors in the cycle format are used to create a test program at step 23. This test program is executed on the tester to evaluate the response outputs of IC.
Converting the IC simulation vectors from the VCD format to the cyclized format is very time consuming, complex and error-prone. This problem is further compounded by the fact that every tester has it's own unique and proprietary language and vector format (ex. TDL and LPAT by Advantest). Subsequently, all this effort in vector conversion becomes extremely time consuming and costly. The time required to process these vectors has grown proportionately with the size of the vectors, taking as much as a month to process all VCD files into cyclized format.
This lengthy process also impedes the ability to process new or improved vectors quickly, thereby slowing the test and debug process. Moreover, the very act of converting original IC simulation vectors into a tester's cyclized format endangers the accuracy of data. This results in errors and test vectors that are no longer simulation-faithful. All these problems result in additional time and cost.
Therefore, there is an urgent need in the industry for a semiconductor IC test system that operates in the IC design environment and eliminates all the complexity involved in the test data conversion into cyclized form as it is done by today's test systems.